Demand for wireless communication devices, such as portable telephones for use in cellular and Personal Communications Service (PCS) systems, is continually increasing. In a typical portable telephone or other wireless receiver, an input analog signal is received and eventually converted to the digital domain for further processing. In order to reduce the amount of required analog circuitry and thereby provide a higher level of circuit integration in the receiver, it is generally desirable to provide the conversion to the digital domain as close as possible to the analog signal input. A conventional technique involves down-converting an input radio frequency (RF) analog signal to an intermediate frequency (IF) analog signal by mixing it with a local oscillator (LO), and then converting the analog IF signal to the digital domain using sigma-delta modulators. However, this approach often requires that the IF signal frequency be very high, such that RF bandpass filter requirements can be relaxed and the need for a second set of IF demodulation circuitry can be avoided. This places a heavy demand on the analog circuitry, and may prevent desired performance measures from being achieved in important applications.
FIG. 1 shows a conventional second-order single-channel bandpass sigma-delta modulator 10. The modulator 10 receives an IF signal on input 12 from an RF downconverter, which is not shown. The IF signal is sampled using a switch 14 which operates at a rate of f.sub.sp of exactly four times the IF signal frequency. The sampled IF signal is applied to a first subtractor 16, a first resonator 18, a second subtractor 20 and a second resonator 22. The output of the second resonator 22 is applied to a comparator 24, the output of which drives first and second multipliers 26 and 28. The output of the comparator 24 is also applied to a 1-bit digital-to-analog (D/A) converter 30. The output of the converter 30 drives inputs of the first and second subtractors 16, 20. The output of the comparator 24 is a stream of bits representative of the incoming analog signal. The in-phase (I) and quadrature (Q) components of the analog signal are extracted by multiplying the bit stream at the output of the comparator 24 by the bit sequences (1 0-1 0 . . . ) and (0 1 0-1 1 . . . ) in multipliers 26 and 28, respectively. The conventional sigma-delta modulator 10 is limited by the maximum sampling rate f.sub.sp to operation at only relatively low IF signal frequencies.
One approach to reducing the maximum sampling rate and thereby increasing the IF operating frequency involves separating a given sigma-delta modulator into two parallel channels, one channel for processing the even samples, and the other channel for processing the odd samples. This approach allows the maximum sampling rate to be decreased by a factor of two. Exemplary two-channel sigma-delta modulators for use in IF sampling receivers are described in A. K. Ong and B. A. Wooley,"A Two-Path Bandpass .SIGMA..DELTA. Modulator for Digital IF Extraction at 20 MHz," 1997 IEEE International Solid-State Circuits Conference, ISSCC '97, Paper FP 13.3, 1997, which is incorporated by reference herein. The technique described in this reference provides some improvement in the maximum IF operating frequency of a sigma-delta modulator in an IF sampling receiver by utilizing two parallel channels, thereby reducing by a factor of one-half the maximum sampling rate at which any particular channel needs to operate. However, this reference does not provide a general approach which permits a given channel of a single-channel or two-channel sigma-delta modulator to be separated into multiple parallel channels. Moreover, the resulting sigma-delta modulators generally include no more than two parallel channels. In addition, these and other conventional approaches fail to provide any techniques for correcting mismatches between multiple channels of a given sigma-delta modulator, and thus do not provide sufficiently accurate performance in many important applications.
It is therefore apparent that a need exists for an improved technique for implementing sigma-delta modulators in a sampling receiver, such that any desired number of parallel branches can be provided for a given channel, and mismatch between different channels can be corrected in an efficient manner.